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sep.1998 6.0 introduction to intelligent power modules (ipm) mitsubishi intelligent power mod- ules (ipms) are advanced hybrid power devices that combine high speed, low loss igbt s with opti- mized gate drive and protection cir- cuitry . highly ef fective over-current and short-circuit protection is real- ized through the use of advanced current sense igbt chips that al- low continuous monitoring of power device current. system reliability is further enhanced by the ipm s inte- grated over temperature and under voltage lock out protection. com- pact, automatically assembled in- telligent power modules are de- signed to reduce system size, cost, and time to market. mitsubishi electric introduced the first full line of intelligent power modules in no- vember , 1991. continuous im- provements in power chip, packag- ing, and control circuit technology have lead to the ipm lineup shown in t able 6.1. 6.0.1 third generation intelli- gent power modules mitsubishi third generation intelli- gent power module family shown in t able 6.1 represents the industries most complete line of ipms. since their original introduction in 1993 the series has been expanded to include 36 types with ratings rang- ing from 10a 600v to 800a 1200v . the power semiconductors used in these modules are based on the field proven h-series igbt and di- ode processes. in t able 6.1 the third generation family has been di- vided into two groups, the low profile series and high power series based on the packaging technology that is used. the third generation ipm has been optimized for minimum switching losses in or- der to meet industry demands for acoustically noiseless inverters with carrier frequencies up to 20khz. the built in gate drive and protection has been carefully de- signed to minimize the components required for the user supplied inter- face circuit. 6.0.2 v -series high power ipms the v -series ipm was developed in order to address newly emerging industry requirements for higher re- liability , lower cost and reduced emi. by utilizing the low inductance packaging technology developed for the u-series igbt module (de- scribed in section 4.1.5) combined with an advanced super soft free- wheel diode and optimized gate drive and protection circuits the v - series ipm family achieves im- proved performance at reduced cost. the detailed descriptions of ipm operation and interface re- quirements presented in sections 6.1 through 6.8 apply to v -series as well as third generation ipms. the only exception being that v - series ipms have a unified short circuit protection function that takes the place of the separate short cir- cuit and over current functions de- scribed in sections 6.4.4 and 6.4.5. the unified protection was made third generation low profile series - 600v pm10csj060 10 six igbt s pm15csj06 0 15 six igbt s PM20CSJ060 20 six igbt s pm30csj060 30 six igbt s pm50rsk060 50 six igbt s + brake ckt. pm75rsk060 75 six igbt s + brake ckt. third generation low profile series - 1200v pm10czf120 10 six igbt s pm10rsh120 10 six igbt s + brake ckt. pm15czf120 15 six igbt s pm15rsh120 15 six igbt s + brake ckt. pm25rsk120 25 six igbt s + brake ckt. third generation high power series - 600v pm75rsa060 75 six igbt s + brake ckt. pm100csa060 100 six igbt s pm100rsa060 100 six igbt s + brake ckt. pm150csa060 150 six igbt s pm150rsa060 150 six igbt s + brake ckt. pm200csa060 200 six igbt s pm200rsa060 200 six igbt s + brake ckt. pm200dsa060 200 t wo igbt s: half bridge pm300dsa060 300 t wo igbt s: half bridge pm400das060 400 t wo igbt s: half bridge pm600dsa060 600 t wo igbt s: half bridge pm800hsa060 800 one igbt third generation high power series - 1200v pm25rsb120 25 six igbt s + brake ckt. pm50rsa120 50 six igbt s + brake ckt. pm75csa120 75 six igbt s pm75dsa120 75 t wo igbt s: half bridge pm100csa120 100 six igbt s pm100dsa120 100 t wo igbt s: half bridge pm150dsa120 150 t wo igbt s: half bridge pm200dsa120 200 t wo igbt s: half bridge pm300dsa120 300 t wo igbt s: half bridge pm400hsa120 400 t wo igbt s: half bridge pm600hsa120 600 one igbt pm800hsa120 800 one igbt v -series high power - 600v pm75r v a060 75 six igbt s + brake ckt. pm100cv a060 100 six igbt s pm150cv a060 150 six igbt s pm200cv a060 200 six igbt s pm300cv a060 300 six igbt s pm400dv a060 400 t wo igbt s: half bridge pm600dv a060 600 t wo igbt s: half bridge v -series high power - 1200v pm50r v a120 50 six igbt s + brake ckt. pm75cv a120 75 six igbt s pm100cv a120 100 six igbt s pm150cv a120 150 six igbt s pm200dv a120 200 t wo igbt s: half bridge pm300dv a120 300 t wo igbt s: half bridge t ype number amps power circuit t ype number amps power circuit t able 6.1 mitsubishi intelligent power modules mitsubishi semiconduct ors power modules mos using intelligent power modules
sep.1998 possible by an advanced rtc (real time control) current clamp- ing circuit that eliminates the need for the over current protection func- tion. in v-series ipms a unified short circuit protection with a delay to avoid unwanted operation re- places the over current and short circuit modes of the third genera- tion devices. 6.1 structure of intelligent power modules mitsubishi intelligent power mod- ules utilize many of the same field proven module packaging tech- nologies used in mitsubishi igbt modules. cost effective implemen- tation of the built in gate drive and protection circuits over a wide range of current ratings was achieved using two different pack- aging techniques. low power de- vices use a multilayer epoxy isola- tion system while medium and high power devices use ceramic isola- tion. these packaging technologies are described in more detail in sec- tions 6.1.1 and 6.1.2. ipm are available in four power circuit con- figurations, single (h), dual (d), six pack (c), and seven pack (r). table 6.1 indicates the power cir- cuit of each ipm and figure 6.1 shows the power circuit configura- tions. 6.1.1 multilayer epoxy construc- tion low power ipm (10-50a, 600v and 10-15a, 1200v) use a multilayer epoxy based isolation system. in this system, alternate layers of cop- per and epoxy are used to create a shielded printed circuit directly on the aluminum base plate. power chips and gate control circuit com- ponents are soldered directly to the substrate eliminating the need for a separate printed circuit board and ceramic isolation materials. mod- ules constructed using this tech- nique are easily identified by their extremely low profile packages. this package design is ideally suited for consumer and industrial applications where low cost and compact size are important. figure 6.2 shows a cross section of this type of ipm package. figure 6.3 is a PM20CSJ060 20a, 600v ipm. p uvw c2e1 c1 e2 e c n type c type d type h p n u type r v w b figure 6.2 multi-layer epoxy construction figure 6.1 power circuit configuration figure 6.3 PM20CSJ060 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. case epoxy resin input signal terminal smt resistor gate control ic smt capacitor igbt chip free-wheel diode chip bond wire copper block baseplate with epoxy based isolation 11 10 9 8 6 7 1 2 3 4 5 mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.1.2 ceramic isolation con- struction higher power ipms are constructed using ceramic isolation material. a direct bond copper process in which copper patterns are bonded directly to the ceramic substrate without the use of solder is used in these modules. this substrate pro- vides the improved thermal charac- teristics and greater current carry- ing capabilities that are needed in these higher power devices. gate drive and control circuits are con- tained on a separate pcb mounted directly above the power devices. the pcb is a multilayer construc- tion with special shield layers for emi noise immunity. figure 6.4 shows the structure of a ceramic isolated intelligent power module. figure 6.5 is a pm75rsa060 75 a, 600v ipm. figure 6.4 ceramic isolation construction figure 6.5 pm75rsa060 silicon chip dbc plate base plate silicon gel case main terminal epoxy resin guide pin input signal terminal interconnect terminal electrode aluminum wire shield layer resistor control board pcb shield layer signal trace mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.1.3 v-series ipm construction v-series ipms are similar to the ce- ramic isolated types described in section 6.1.2 except that an in- sert molded case similar to the u-series igbt is used. like the u-series igbt described in sec- tion 4.1.5, the v-series ipm has lower internal inductance and improved power cycle durability. figure 6.6 is a cross section draw- ing showing the construction of the v-series ipm. the insert molded case makes the v-series ipm is easier to manufacture and lower in cost. figure 6.7 shows a pm150cva120 which is a 150a 1200v v-series ipm. 6.1.4 advantages of intelligent power module ipm (intelligent power module) products were designed and devel- oped to provide advantages to customers by reducing design, de- velopment, and manufacturing costs as well as providing improve- ment in system performance and reliability over conventional igbts. design and development effort is simplified and successful drive co- ordination is assured by the inte- gration of the drive and protection circuitry directly into the ipm. re- duced time to market is only one of the additional benefits of using an ipm. others include increased sys- tem reliability through automated ipm assembly and test and reduc- tion in the number of components that must be purchased, stored, and assembled. often the system size can be reduced through smaller heatsink requirements as a result of lower on-state and switch- ing losses. all ipms use the same standardized gate control interface with logic level control circuits al- lowing extension of the product line without additional drive circuit de- sign. finally, the ability of the ipm to self protect in fault situations re- duce the chance of device destruc- tion during development testing as well as in field stress situations. 6.2 ipm ratings and characteris- tics ipm datasheets are divided into three sections: ? maximum ratings ? characteristics (electrical, thermal, mechanical) ? recommended operating conditions the limits given as maximum rating must not be exceeded under any circumstances, otherwise destruc- tion of the ipm may result. key parameters needed for system design are indicated as electrical, thermal, and mechanical character- istics. the given recommended operating conditions and application circuits should be considered as a prefer- able design guideline fitting most applications. power terminals silicone gel cover insert mold case dbc ain ceramic substrate silicon chips base plate printed circuit board aluminum bond wires signal terminals figure 6.6 v-series ipm construction figure 6.7 pm150cva120 mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.2.1 maximum ratings symbol parameter definition inverter part v cc supply voltage maximum dc bus voltage applied between p-n v ces collector-emitter voltage maximum off-state collector-emitter voltage at applied control input off signal i c collector-current maximum dc collector and fwdi current @ t j 150 c i cp collector-current (peak) maximum peak collector and fwdi current @ t j 150 c p c collector dissipation maximum power dissipation per igbt switch at t j = 25 c t j junction temperature range of igbt junction temperature during operation brake part v r(dc) fwdi reverse voltage maximum reverse voltage of fwdi i f fwdi forward current maximum fwdi dc current at t j 150 c control part v d supply voltage maximum control supply voltage v cin input voltage maximum voltage between input (i) and ground (c) pins v fo fault output supply voltage maximum voltage between fault output (fo) and ground (c) pins i fo fault output current maximum sink current of fault output (fo) pin total system v cc(prot) supply voltage protected maximum dc bus voltage applied between p-n with guaranteed oc and sc protection by oc & sc t c module case operating range of allowable case temperature at specified reference point during operation temperature t stg storage temperature range of allowable ambient temperature without voltage or current v iso isolation voltage maximum isolation voltage (ac 60hz 1 min.) between baseplate and module terminals (all main and signal terminals externally shorted together) 6.2.2 thermal resistance symbol parameter definition r th(j-c) junction to case maximum value of thermal resistance between junction and case per switch thermal resistance r th(c-f) contact thermal maximum value of thermal resistance between case and fin (heatsink) per igbt/fwdi pair resistance with thermal grease applied according to mounting recommendations 6.2.3 electrical characteristics symbol parameter definition inverter and brake part v ce (sat) collector-emitter igbt on-state voltage at rated collector current under specified conditions saturation voltage v ec fwdi forward voltage fwdi forward voltage at rated current under specified conditions t on turn-on time t rr fwdi recovery time inductive load switching times under rated conditions t c(on) turn-on crossover time (see figure 6.10) t off turn-off time t c(off) turn-off crossover time i ces collector-emitter cutoff collector-emitter current in off-state at v ce = v ces under specified conditions mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 the following test circuits are used to evaluate the ipm characteristics. 1. v ce (sat) and v ec to ensure specified junction temperature, t j, measurements of v ce (sat) and v ec must be performed as low duty factor pulsed tests. (see figures 6.8 and 6.9) 6.2.3 electrical characteristics (continued) symbol parameter definition control part v d supply voltage range of allowable control supply voltage in switching operation i d circuit current control supply current in stand-by mode v cin(on) input on-voltage a voltage applied between input (i) and ground (c) pins less than this value will turn on the ipm v cin(off) input off-voltage a voltage applied between input (i) and ground (c) pins higher than this value will turn off the ipm f pwm pwm input frequency range of pwm frequency for vvvf inverter operations t dead arm shoot through time delay required between high and low side input off/on signals to prevent an blocking time arm shoot through oc over-current trip level collector that will activate the over-current protection sc short-circuit trip level collector current that will activate the short-circuit protection t off(oc) over-current delay time time delay after collector current exceeds oc trip level until oc protection is activated ot over-temperature trip level baseplate temperature that will activate the over-temperature protection ot r over-temperature temperature that the baseplate must fall below to reset an over-temperature fault reset level uv control supply control supply voltage below this value will activate the undervoltage protection undervoltage trip level uv r control supply control supply voltage that must exceed to reset an undervoltage fault undervoltage reset level i fo(h) fault output inactive current fault output sink current when no fault has occurred i fo(l) fault output active current fault output sink current when a fault has occurred t fo fault output pulsed width duration of the generated fault output pulse v sxr sxr terminal output voltage regulated power supply voltage on sxr terminal for driving the external optocoupler 6.2.4 recommended operation conditions symbol parameter definition v cc main supply voltage recommended dc bus voltage range v d control supply voltage recommended control supply voltage range v cin(on) input on-voltage recommended input voltage range to turn on the ipm v cin(off) input off-voltage recommended input voltage range to turn off the ipm f pwm pwm input frequency recommended range of pwm carrier frequency using the recommended application circuit t dead arm shoot through recommended time delay between high and low side off/on signals to the optocouplers blocking time using the recommended application circuit vx1 sxr cx1 vxc e1(e2) c1(c2) v d v i c vx1 sxr cx1 vxc e1(e2) c1(c2) v d v i c figure 6.8 v ce (sat) test figure 6.9 v ec test 6.2.5 test circuits and conditions mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 2. half-bridge test circuit and switching time definitions. figure 6.10 shows the stan- dard half-bridge test circuit and switching waveforms. switch- ing times and fwdi recovery characteristics are defined as shown in this figure. 3. overcurrent and short-circuit test i trip levels and timing specifica- tions in short circuit and overcurrent are defined as shown in figure 6.11. by using a fixed load resistance the sup- ply voltage, v cc , is gradually increased until oc and sc trip levels are reached. precautions: a. before applying any main bus voltage, v cc , the input termi- nals should be pulled up by re- sistors to their corresponding control supply (or sxr) pin, each input signal should be kept in off state, and the con- trol supply should be provided. after this, the specified on and off level for each input signal should be applied. the control supply should also be applied to the non-operating arm of the module under test and inputs of these arms should be kept to their off state. b. when performing oc and sc tests the applied voltage, v cc , must be less than v cc(prot) and the turn-off surge voltage spike must not be allowed to rise above the v ces rating of the device. (these tests must not be attempted using a curve tracer.) + i c integrated gate control circuit integrated gate control circuit + + t d (on) i cin (t on = t d ( on ) + t r ) t r t d (off) (t off = t d (off) + t f ) t f t c (off) t c (on) 10% 90% 10% 90% i c t rr i rr v ce i c v ce off signal on pulse v cc v d v d figure 6.10 half-bridge test circuit and switching time definitions on pulse sc oc input signal normal operation over current short circuit v c on pulse r* r is sized to cause sc and oc conditions * v cc + t off (oc) i c integrated gate control circuit sc oc sc oc i c i c i c figure 6.11 over-current and short-circuit test circuit mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.3 area of safe operation for intelligent power modules the ipms built-in gate drive and protection circuits protect it from many of the operating modes that would violate the safe operation area (soa) of non-intelligent igbt modules. a conventional soa defi- nition that characterizes all pos- sible combinations of voltage, cur- rent, and time that would cause power device failure is not re- quired. in order to define the soa for ipms, the power device capabil- ity and control circuit operation must both be considered. the re- sulting easy to use short circuit and switching soa definitions for intelli- gent power modules are summa- rized in this section. 6.3.1 switching soa switching or turn-off soa is nor- mally defined in terms of the maxi- mum allowable simultaneous volt- age and current during repetitive turn-off switching operations. in the case of the ipm the built-in gate drive eliminates many of the dan- gerous combinations of voltage and current that are caused by im- proper gate drive. in addition, the maximum operating current is lim- ited by the over current protection circuit. given these constraints the switching soa can be defined us- ing the waveform shown in figure 6.12. this waveform shows that the ipm will operate safely as long as the dc bus voltage is below the data sheet v cc(prot) specification, the turn-off transient voltage across c-e terminals of each ipm switch is maintained below the v ces specifi- cation, t j is less than 125 c, and the control power supply voltage is between 13.5v and 16.5v. in this waveform i oc is the maximum cur- rent that the ipm will allow without causing an over current (oc) fault to occur. in other words, it is just below the oc trip level. this wave- form defines the worst case for hard turn-off operations because the ipm will initiate a controlled slow shutdown for currents higher than the oc trip level. 6.3.2 short circuit soa the waveform in figure 6.13 de- picts typical short circuit operation. the standard test condition uses a minimum impedance short circuit which causes the maximum short circuit current to flow in the device. in this test, the short circuit current (i sc ) is limited only by the device characteristics. the ipm is guaran- teed to survive non-repetitive short circuit and over current conditions as long as the initial dc bus volt- age is less than the v cc(prot) specification, all transient voltages across c-e terminals of each ipm switch are maintained less than the v ces specification, t j is less than 125 c, and the control supply volt- age is between 13.5v and 16.5v. the waveform shown depicts the controlled slow shutdown that is used by the ipm in order to help minimize transient voltages. note: the condition v ce v ces has to be carefully checked for each ipm switch. for easing the design an- other rating is given on the data sheets, v cc(surge) , i.e., the maxi- mum allowable switching surge voltage applied between the p and n terminals. 6.3.3 active region soa like most igbts, the igbts used in the ipm are not suitable for linear or active region operation. nor- mally device capabilities in this mode of operation are described in terms of fbsoa (forward biased safe operating area). the ipms internal gate drive forces the igbt to operate with a gate voltage of ei- ther zero for the off state or the control supply voltage (v d ) for the on state. the ipms under-voltage lock out prevents any possibility of active or linear operation by auto- matically turning the power device off if v d drops to a level that could cause desaturation of the igbt. figure 6.13 short-circuit operation figure 6.12 turn-off waveform i oc v ces v cc(prot) t off(oc) v ces v ces v cc(prot) i sc mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.4. ipm self protection 6.4.1 self protection features ipm (intelligent power modules) have sophisticated built-in protec- tion circuits that prevent the power devices from being damaged should the system malfunction or be over stressed. our design and applications engineers have devel- oped fault detection and shut down schemes that allow maximum utili- zation of power device capability without compromising reliability. control supply under-voltage, over- temperature, over-current, and short-circuit protection are all pro- vided by the ipm's internal gate control circuits. a fault output signal is provided to alert the system con- troller if any of the protection cir- cuits are activated. figure 6.14 is a block diagram showing the ipms internally integrated functions. this diagram also shows the isolated in- terface circuits and control power supply that must be provided by the user. the internal gate control circuit requires only a simple +15v dc supply. specially designed gate drive circuits eliminate the need for a negative supply to off bias the igbt. the ipm control input is de- signed to interface with optocoupled transistors with a mini- mum of external components. the operation and timing of each pro- tection feature is described in sec- tions 6.4.2 through 6.4.5. 6.4.2 control supply under-voltage lock-out the intelligent power module's in- ternal control circuits operate from an isolated 15v dc supply. if, for any reason, the voltage of this sup- ply drops below the specified un- der-voltage trip level (uv t ), the power devices will be turned off and a fault signal will be generated. small glitches less than the speci- fied t duv in length will not affect the operation of the control circuitry and will be ignored by the under- voltage protection circuit. in order for normal operation to resume, the supply voltage must exceed the un- der-voltage reset level (uv r ). op- eration of the under-voltage protec- tion circuit will also occur during power up and power down of the control supply. this operation is normal and the system controller's program should take the fault out- put delay (t fo ) into account. figure 6.15 is a timing diagram showing the operation of the under-voltage lock-out protection circuit. in this diagram an active low input signal is applied to the input pin of the ipm by the system controller. the effects of control supply power up, power down and failure on the power device gate drive and fault output are shown. caution: 1. application of the main bus voltage at a rate greater than 20v/ m s before the control power supply is on and stabi- lized may cause destruction of the power devices. 2. voltage ripple on the control power supply with dv/dt in ex- cess of 5v/ m s may cause a false trip of the uv lock-out. 6.4.3 over-temperature protection the intelligent power module has a temperature sensor mounted on the isolating base plate near the igbt chips. if the temperature of the base plate exceeds the over- temperature trip level (ot) the ipms internal control circuit will protect the power devices by dis- abling the gate drive and ignoring the control input signal until the over temperature condition has subsided. in six and seven pack modules all three low side devices will be turned off and a low side fault signal will be generated. high side switches are unaffected and can still be turned on and off by the system controller. similarly, in dual type modules only the low side de- vice is disabled. the fault output will remain as long as the over- temperature condition exists. when the temperature falls below the over-temperature reset level (ot r ), and the control input is high (off- state) the power device will be en- abled and normal operation will re- sume at the next low (on) input sig- nal. figure 6.16 is a timing diagram showing the operation of the over- gate control circuit gate drive over temp uv lock-out over current short circuit isolated power supply isolating interface circuit isolating interface circuit current sense igbt temperature sensor sense current intelligent power module input signal fault output collector emitter figure 6.14 ipm functional diagram mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 temperature protection circuit. the over temperature function pro- vides effective protection against overloads and cooling system fail- ures in most applications. however, it does not guarantee that the maxi- mum junction temperature rating of the igbt chip will never be ex- ceeded. in cases of abnormally high losses such as failure of the system controller to properly regu- late current or excessively high switching frequency it is possible for igbt chip to exceed t j(max) be- fore the base plate reaches the ot trip level. caution: tripping of the over-temperature protection is an indication of stress- ful operation. repetitive tripping should be avoided. 6.4.4 over-current protection the ipm uses current sense igbt chips to continuously monitor power device current. if the current though the intelligent power mod- ule exceeds the specified overcurrent trip level (oc) for a pe- riod longer than t off(oc) the ipms internal control circuit will protect the power device by disabling the gate drive and generating a fault output signal. the timing of the over-current protection is shown in figure 6.17. the t off(oc) delay is implemented in order to avoid trip- ping of the oc protection on short pulses of current above the oc level that are not dangerous for the power device. when an over-cur- rent is detected a controlled shut- down is initiated and a fault output is generated. the controlled shut- down lowers the turn-off di/dt which helps to control transient voltages that can occur during shut down from high fault currents. most intelligent modules use the two step shutdown depicted in fig- ure 6.17. in the two step shutdown, the gate voltage is reduced to an intermediate voltage causing the current through the device to drop slowly to a low level. then, about 5 m s later, the gate voltage is re- duced to zero completing the shut down. some of the large six and seven pack ipms use an active ramp of gate voltage to achieve the desired reduction in turn off di/dt under high fault currents. the oscil- lographs in figure 6.18 illustrate figure 6.15 operation of under-voltage lockout input signal base plate temperature (tb) fault output current (i fo ) internal gate voltage v ge ot ot r figure 6.16 operation of over-temperature input signal control supply voltage fault output current (i fo ) internal gate voltage v ge control supply on short glitch ignored power supply fault and recovery control supply off uv r uv t t fo t duv t fo t duv mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 the effect of the controlled shut- down (for obtaining the oscillo- graph in a the internal soft shutdown was in- tentionally deactivated). the ipm uses actual device current mea- surement to detect all types of over current conditions. even resistive and inductive shorts to ground that are often missed by conventional desaturation and bus current sens- ing protection schemes will be de- tected by the ipms current sense igbts. note: v-series ipms do not have an over- current protection function. instead a unified short circuit pro- tection function that has a delay like the over current protection de- scribed in this section is used. normal operation fwd recovery current ignored by oc protection over current fault and recovery short circuit fault and recovery normal operation t fo t fo t hold t hold t off (oc) input signal internal gate voltage (v ge ) short circuit trip level over circuit trip level collector current i fo fault output current figure 6.17 operation of over-current and short-circuit protection oc protection without soft shutdown v ce (surge) oc protection with soft shutdown i c v ce i c v ce v ce (surge) figure 6.18 oc operation of pm200dsa060 (i c : 100a/div; 100v/div; t: 1 m s/div) mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.4.5 short circuit protection if a load short circuit occurs or the system controller malfunctions causing a shoot through, the ipms built in short circuit protection will prevent the igbts from being dam- aged. when the current, through the igbt exceeds the short circuit trip level (sc), an immediate con- trolled shutdown is initiated and a fault output is generated. the same controlled shutdown techniques used in the over current protection are used to help control transient voltages during short circuit shut down. the short circuit protection provided by the ipm uses actual current measurement to detect dangerous conditions. this type of protection is faster and more reli- able than conventional out-of-satu- ration protection schemes. figure 6.17 is a timing diagram showing the operation of the short circuit protection. to reduce the response time be- tween sc detection and sc shut- down, a real time current control circuit (rtc) has been adopted. the rtc bypasses all but the final stage of the igbt driver in sc op- eration thereby reducing the re- sponse time to less than 100ns. the oscillographs in figure 6.19 il- lustrate the effectiveness of the rtc technique by comparing short circuit operation of second genera- tion ipm (without rtc) and third generation ipm (with rtc). a significant improvement can be seen as the power stress is much lower as the time in short circuit and the magnitude of the short cir- cuit current are substantially re- duced. note: the short circuit protection in v-series ipms has a delay similar to the third generation over current protection function described in 6.4.4. the need for a quick trip has been eliminated through the use of a new advanced rtc circuit. caution: 1. tripping of the over current and short circuit protection indi- cates stressful operation of the igbt. repetitive tripping must be avoided. 2. high surge voltages can occur during emergency shutdown. low inductance buswork and snubbers are recommended. 6.5 ipm selection there are two key areas that must be coordinated for proper selection of an ipm for a particular inverter application. these are peak current coordination to the ipm overcurrent trip level and proper thermal design to ensure that peak junction temperature is al- ways less than the maximum junc- tion temperature rating (150 c) and that the baseplate temperature remains below the over-temperature trip level. 6.5.1 coordination of oc trip peak current is addressed by refer- ence to the power rating of the mo- tor. tables 6.2, 6.3 and 6.4 give recommended ipm types derived from the oc trip level and the peak motor current requirement based on several assumptions for the in- verter and motor operation regard- ing efficiency, power factor, maxi- mum overload, and current ripple. for the purposes of this table, the maximum motor current is taken from the nec table. this already includes the motor efficiency and power factor appropriate to the par- ticular motor size. peak inverter current is then calculated using this rms current, a 200% overload re- quirement, and a 20% ripple factor. an ipm is then selected which has a minimum overcurrent trip level that is above this calculated peak operating requirement. figure 6.19 waveforms showing the effect of the rtc circuit short circuit operation without rtc circuit 100a, 600v, ipm short circuit operation with rtc circuit 100a, 600v, ipm 800a v ce i c i c =200a/div, v ce =100v/div, t=1s/div v ce t i c t 410a i c =200a/div, v ce =100v/div, t=1s/div t t mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 table 6.2 motor rating vs. oc protection (230 vac line) current motor rating (hp) nec current rating a(rms) t inverter peak current (a)* applicable ipm minimum oc trip (a) 0.5 2.0 6.8 pm10csj060 12 0.75 2.8 9.5 pm10csj060 12 1 3.6 12.2 pm15csj060 18 1.5 5.2 17.6 pm15csj060 18 2 6.8 23 PM20CSJ060 28 3 9.6 32 pm30csj060, pm30rsf060 39 5 15.2 52 pm50rsa060, pm50rsk060 65 7.5 22 75 pm75rsa060, pm75rsk060 115 10 28 95 pm75rsa060, pm75rsk060 115 15 42 143 pm100csa060, pm100rsa060 158 20 54 183 pm150csa060, pm150rsa060 210 25 68 231 pm200csa060, pm200rsa060, 310 pm200dsa060 x3 30 80 271 pm200csa060, pm200rsa060, 310 pm200dsa060 x3 40 104 353 pm300dsa060 x3 390 50 130 441 pm400dsa060 x3 500 60 154 523 pm600dsa060 x3 740 75 192 652 pm600dsa060 x3 740 100 256 869 pm800hsa060 x6 1000 t - from nec table 430-150 * - inverter peak current is based on 200% overload requirement and a 20% current ripple factor. table 6.3 motor rating vs. oc protection (460 vac line) current motor rating (hp) nec current rating a(rms) t inverter peak current (a)* applicable ipm minimum oc trip (a) 0.5 1.0 3.4 pm10rsh120, pm10czf120 15 0.75 1.4 4.8 pm10rsh120, pm10czf120 15 1 1.8 6.1 pm10rsh120, pm10czf120 15 1.5 2.6 8.8 pm10rsh120, pm10czf120 15 2 3.4 12 pm10rsh120, pm10czf120 15 3 4.8 16 pm15rsh120, pm15czf120 22 5 7.6 26 pm25rsb120, pm25rsk120 32 7.5 11 37 pm50rsa120 59 10 14 48 pm50rsa120 59 15 21 71 pm75csa120, pm75dsa120 x3 105 20 27 92 pm75csa120, pm75dsa120 x3 105 25 34 115 pm100csa120, pm100dsa120 x3 145 30 40 136 pm100csa120, pm100dsa120 x3 145 40 52 176 pm150dsa120 x3 200 50 65 221 pm200dsa120 x3 240 60 77 261 pm300dsa120 x3 380 75 96 326 pm300dsa120 x3 380 100 124 421 pm400hsa120 x6 480 125 156 529 pm600hsa120 x6 740 150 180 611 pm600hsa120 x6 740 200 240 815 pm800hsa120 x6 1060 250 300 1020 pm800hsa120 x6 1060 t - from nec table 430-150 * - inverter peak current is based on 200% overload requirement and a 20% current ripple factor. mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.5.2 estimating losses once the coordination of the oc trip with the application require- ments has been established the next step is determining the cooling system requirements. section 3.4 provides a general description of the methodology for loss estimation and thermal system design. figure 6.20 shows the total switching en- ergy (e sw(on) +e sw(off) ) versus i c for all third generation ipms. figure 6.21 shows total switching energy versus i c for v-series ipms. a detailed explanation of these curves and their use can be found in section 3.4.1. figures 6.22 through 6.34 show simulation results calculating total power loss (switching and conduction) per arm in a sinusoidal output pwm inverter application using v-series ipms. table 6.4 motor rating vs. sc protection for v-series ipms current motor rating (hp) nec current rating a(rms) t inverter peak current (a)* applicable ipm minimum sc trip (a) 240vac line 10 28 95 pm75rva060 115 15 42 143 pm100cva060 158 20 54 183 pm150cva060 210 30 80 271 pm200cva060 310 40 104 353 pm300cva060 396 50 130 441 pm400dva060 650 75 192 652 pm600dva060 1000 460vac line 10 14 48 pm50rva120 59 20 27 92 pm75cva120 105 30 40 136 pm100cva120 145 40 52 176 pm150cva120 200 50 65 221 pm200dva120 240 75 96 326 pm300dva120 380 t - from nec table 430-150 * - inverter peak current is based on 200% overload requirement and a 20% current ripple factor. 10 0 10 1 10 2 10 3 10 4 10 -1 10 0 collector current, i c , (amperes) switchintg dissipation, (mj/pulse) 10 1 10 3 10 2 conditions: inductive load switching operation t j = 125 o c v cc = 1/2 v ces v d = 15v switching dissipation = turn-on dissipation + turn-off dissipation compatible i c range: rated i c 0.1 ~ 1.4 600v series 1200v series applicable types: third-generation ipm pm200dsa060, pm75dsa120, pm300dsa120, pm75csa120, PM20CSJ060, pm50rsk060, pm10rsh120, pm300dsa060, pm100dsa120, pm100csa060, pm100csa120, pm300csj060, pm75rsa060, pm15rsh120, pm400dsa060, pm150dsa120, pm150csa060, pm10csj060, pm30rsf060, pm100rsa060, pm25rsb120, pm600dsa060, pm200dsa120, pm200csa060, pm15csj060, pm50rsa060, pm150rsa060, pm50rsa120 figure 6.20 switching energy vs. i c for third generation ipms mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 10 0 10 1 10 2 10 3 10 4 10 -1 10 0 collector current, i c , (amperes) switching energy loss for v-series ipms switching energy, (mj/pulse) 10 1 10 3 10 2 conditions: inductive load t j = 125 o c v cc = 1/2 v ces v d = 15v 600v series 1200v series e sw (on) + e sw (off) compatible i c range: rated i c 0.1 ~ 1.4 0 20 40 60 100 80 120 0 i o (arms) 50 p(w) 100 150 200 250 dc loss sw loss total loss v cc = 300v v d = 15v t j = 125?c p.f. = 0.8 fc = 10khz figure 6.21 figure 6.22 power loss simulation of pm75rva060 (typ.) figure 6.23 power loss simulation of pm100cva060 (typ.) figure 6.24 power loss simulation of pm150cva060 (typ.) figure 6.25 power loss simulation of pm200cva060 (typ.) figure 6.27 power loss simulation of pm400dva060 (typ.) figure 6.28 power loss simulation of pm600dva060 (typ.) figure 6.26 power loss simulation of pm300cva060 (typ.) figure 6.29 power loss simulation of pm50rva120 (typ.) 0 20 40 60 100 80 120 0 i o (arms) 50 p(w) 100 150 200 250 dc loss sw loss total loss v cc = 300v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 20 40 60 100 80 120 0 i o (arms) 50 p(w) 100 150 200 250 dc loss sw loss total loss v cc = 300v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 40 80 120 200 160 240 0 i o (arms) 50 p(w) 100 150 200 250 dc loss sw loss total loss v cc = 300v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 40 80 120 200 160 240 0 i o (arms) 50 p(w) 100 150 200 250 dc loss sw loss total loss v cc = 300v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 40 80 120 200 160 240 0 i o (arms) 50 p(w) 100 150 200 250 dc loss sw loss total loss v cc = 300v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 40 80 120 200 160 360 320 240 280 0 i o (arms) 50 p(w) 100 150 300 250 200 350 dc loss sw loss total loss v cc = 300v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0153045 90 75 60 0 i o (arms) 50 p(w) 100 150 300 250 200 350 dc loss sw loss total loss v cc = 600v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.6 controlling the intelligent power module ipm (intelligent power modules) are easy to operate. the integrated drive and protection circuits require only an isolated power supply and a low level on/off control signal. a fault output is provided for monitor- ing the operation of the modules in- ternal protection circuits. 6.6.1 the control power supply depending on the power circuit configuration of the module one, two, or four isolated power supplies are required by the ipms internal drive and protection circuits. in high power 3-phase inverters using single or dual type ipms it is good practice to use six isolated power supplies. in these high current ap- plications each low side device must have its own isolated control power supply in order to avoid ground loop noise problems. the control supplies should be regu- lated to 15v +/-10% in order to avoid over-voltage damage or false tripping of the under-voltage pro- tection. the supplies should have an isolation voltage rating of at least two times the ipms v ces rat- ing (i.e. v iso = 2400v for 1200v module). the current that must be supplied by the control power sup- ply is the sum of the quiescent cur- rent needed to power the internal control circuits and the current re- quired to drive the igbt gate. table 6.5 summarizes the typical and maximum control power supply current requirements for figure 6.30 power loss simulation of pm75rva1200 (typ.) figure 6.31 power loss simulation of pm100cva120 (typ.) figure 6.33 power loss simulation of pm200dva120 (typ.) figure 6.34 power loss simulation of pm300dva120 (typ.) figure 6.32 power loss simulation of pm150cva120 (typ.) 0153045 90 75 60 0 i o (arms) 50 p(w) 100 150 300 250 200 350 dc loss sw loss total loss v cc = 600v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 20 40 60 100 80 180 160 120 140 0 i o (arms) 50 p(w) 100 150 300 250 200 350 dc loss sw loss total loss v cc = 600v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 20 40 60 100 80 180 160 120 140 0 i o (arms) 50 p(w) 100 150 300 250 200 350 dc loss sw loss total loss v cc = 600v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 20 40 60 100 80 180 160 120 140 0 i o (arms) 50 p(w) 100 150 300 250 200 350 dc loss sw loss total loss v cc = 600v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz 0 20 40 60 100 80 180 160 120 140 0 i o (arms) 50 p(w) 100 150 300 250 200 350 dc loss sw loss total loss v cc = 600v v d = 15v t j = 125c p.f. = 0.8 fc = 10khz mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 third generation intelligent power modules. table 6.6 summarizes control supply requirements for v-series ipms. these tables give control circuit currents for the qui- escent (not switching) state and for 20khz switching. this data is pro- vided in order to help the user de- sign appropriately sized control power supplies. power requirements for operating frequencies other than 20khz can be determined by scaling the fre- quency dependent portion of the control circuit current. for example, to determine the maximum control circuit current for a pm300dsa120 operating at 7khz the maximum quiescent control circuit current is subtracted from the maximum 20khz control circuit current: 70ma C 30ma = 40ma 40ma is the frequency dependent portion of the control circuit current for 20khz operation. for 7khz operation the frequency dependent portion is: 40ma x (7khz ? 20khz) = 14ma to get the total control power sup- ply current required, the quiescent current must be added back: 30ma + 14ma = 44ma 44ma is the maximum control cir- cuit current required for a pm300dsa120 operating at 7khz. capacitive coupling between pri- mary and secondary sides of isolated control supplies must be minimized as parasitic capaci- tances in excess of 100pf can cause noise that may trigger table 6.5 control power requirements for third generation ipms (v d = 15v, duty = 50%) ma n side p side (each supply) dc 20khz dc 20khz type name typ. max typ. max. typ. max. typ. max. 600v series pm10csj060 18 25 23 32 7 10 8 12 pm15csj060 18 25 23 32 7 10 8 12 PM20CSJ060 18 25 24 34 7 10 8 12 pm30csj060 18 25 24 34 7 10 9 13 pm100csa060 40 55 78 100 13 18 25 34 pm150csa060 40 55 80 110 13 18 25 38 pm200csa060 40 55 85 120 13 18 27 40 pm30rsf060 25 30 32 45 7 10 9 13 pm50rsa060 44 60 70 100 13 18 23 32 pm50rsk060 44 60 70 100 13 18 23 32 pm75rsa060 44 60 75 100 13 18 24 35 pm100rsa060 44 60 78 105 13 18 25 36 pm150rsa060 52 72 72 113 13 18 26 38 pm200rsa060 52 72 85 115 13 18 26 40 pm200dsa060 19 26 30 42 19 26 30 42 pm300dsa060 19 26 35 48 19 26 35 48 pm400dsa060 23 30 40 60 23 30 40 60 pm600dsa060 23 30 50 70 23 30 50 70 pm800hsa060 23 30 50 70 CCCC 1200v series pm10rsh120 25 35 31 44 7 10 9 13 pm10czf120 18 25 7 10 9 13 pm15rsh120 25 35 32 45 7 10 9 13 pm15czf120 18 25 7 10 9 13 pm25rsb120 44 60 60 83 13 18 18 25 pm25rsk120 44 60 60 83 13 18 18 25 pm50rsa120 44 60 65 90 13 18 19 27 pm75csa120 44 60 60 83 13 18 20 28 pm100csa120 40 55 75 104 13 18 25 35 pm75dsa120 13 20 20 28 13 20 20 28 pm100dsa120 19 26 30 42 19 26 30 42 pm150dsa120 19 26 35 48 19 26 35 48 pm200dsa120 23 30 48 67 23 30 48 67 pm300dsa120 23 30 50 70 23 30 50 70 pm400hsa120 23 30 60 90 CCCC pm600jsa120 23 30 60 90 CCCC pm800hsa120 30 40 C C CCCC mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 the control circuits. an electrolytic or tantalum decoupling capacitor should be connected across the control power supply at the ipms terminals. this capacitor will help to filter common noise on the con- trol power supply and provide the high pulse currents required by the ipms internal gate drive circuits. isolated control power supplies can be created using a variety of tech- niques. control power can be de- rived from the main input line using either a switching power supply with multiple outputs or a line fre- quency transformer with multiple secondaries. control power sup- plies can also be derived from the main logic power supply using dc- to-dc converters. using a compact dc-to-dc converter for each iso- lated supply can help to simplify the interface circuit layout. a distrib- uted dc-to-dc converter in which a single oscillator is used to drive several small isolation transformers can provide the layout advantages of separate dc-to-dc converters at a lower cost. in order to simplify the design of the required isolated power sup- plies, mitsubishi has developed two dc-to-dc converter modules to work with the ipms. the m57120l is a high input voltage step down converter. when supplied with 113 to 400vdc the m57120l will pro- duce a regulated 20vdc output. the 20vdc can then be connected to the m57140-01 to produce four isolated 15vdc outputs to power the ipms control circuits. the m57140-01 can also be used as a stand alone unit if 20vdc is avail- able from another source such as the main logic power supply. figure 6.35 shows an isolated interface circuit for a seven pack ipm using m57140-01. figure 6.36 shows a complete high input voltage iso- lated power supply circuit for a dual type intelligent power module. caution: using bootstrap techniques is not recommended because the voltage ripple on vd may cause a false trip of the undervoltage protection in certain inverter pwm modes. 6.6.2 interface circuit require- ments the igbt power switches in the ipm are controlled by a low level input signal. the active low control input will keep the power devices off when it is held high. typically the input pin of the ipm is pulled high with a resistor connected to the positive side of the control power supply. an on signal is then generated by pulling the control in- put low. the fault output is an open collector with its maximum sink cur- rent internally limited. when a fault condition occurs the open collector device turns on allowing the fault output to sink current from the posi- tive side of the control supply. fault and on/off control signals are usu- ally transferred to and from the sys- tem controller using isolating inter- face circuits. isolating interfaces al- low high and low side control sig- nals to be referenced to a common logic level. the isolation is usually provided by optocouplers. how- ever, fiber optics, pulse transform- ers, or level shifting circuits could be used. the most important con- sideration in interface circuit design is layout. shielding and careful routing of printed circuit wiring is necessary in order to avoid cou- pling of dv/dt noise into control cir- cuits. parasitic capacitance be- tween high side table 6.6 v-series ipm control power supply current n side p side (each supply) dc 20khz dc 20khz type name typ. max typ. max. typ. max. typ. max. 600v series pm75rva060 44 60 72 94 13 18 21 27 pm100cva060 40 55 68 88 13 18 22 29 pm150cva060 40 55 72 94 13 18 23 30 pm200cva060 40 55 84 110 13 18 28 36 pm300cva060 52 72 130 170 17 24 43 56 pm400dva060 23 30 56 73 23 30 56 73 pm600dva060 23 30 56 73 23 30 56 73 1200v series pm50rva120 44 60 73 95 13 18 21 27 pm75cva120 40 55 70 92 13 18 24 31 pm100cva120 40 55 80 104 13 18 26 34 pm150cva120 72 100 128 166 24 34 42 55 pm200dva120 37 48 52 68 37 48 52 68 pm300dva120 37 48 52 68 37 48 52 68 mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 1 hcpl4504 0.1 m f seven pack ipm v up1 u p v upc u fo c 1 20k 0.1 m f 20k 2 3 4 8 7 6 5 3 pc817 4 2 1 1 hcpl4504 2 3 4 8 7 6 5 3 pc817 4 1 2 3 4 5 - + + 6 7 8 9 10 11 v in 12 13 14 0 +15 0 +15 0 +15 0 +15 2 1 4 3 2 1 v vp1 v p v vpc v fo v wp1 w p v wpc w fo u n b r v nc v ni f o v n w n 8 7 6 5 12 11 10 9 16 15 14 13 19 18 17 1 hcpl4504 0.1 m f + + 20k 2 3 4 8 7 6 5 3 pc817 4 2 1 c 1 + c 1 + 1 hcpl4504 0.1 m f 4.7k c 2 + 2 3 4 8 7 6 5 1 pc817 2 4 3 1 hcpl4504 0.1 m f 2 3 4 8 7 6 5 1 hcpl4504 0.1 m f 20k 20k 20k 2 3 4 8 7 6 5 3 pc817 4 2 1 20v 330 m f fo n w n v n u n b w p fo wp v p fo vp u p fo up note: for c1 and c2 see section 6.6.3 figure 6.35 isolated interface circuit for seven-pack ipms mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 interface circuits, high and low side interface circuits, or primary and secondary sides of the isolating de- vices can cause noise problems. careful layout of control power supply and isolating circuit wiring is necessary. the following is a list of guidelines that should be followed when designing interface circuits. figure 6.37 shows an example in- terface circuit layout for dual type ipms. figure 6.38 shows an ex- ample interface circuit layout for a v-series ipms.the shielding and printed circuit routing techniques used in this example are intended to illustrate a typical application of the layout guidelines. interface circuit layout guidelines i. maintain maximum interface isolation. avoid routing printed circuit board traces from pri- mary and secondary sides of the isolation device near to or above and below each other. any layout that increases the primary to secondary capaci- tance of the isolating interface can cause noise problems. ii. maintain maximum control power supply isolation. avoid routing printed circuit board traces from up, vp, wp, and n side supplies near to each other. high dv/dts exist be- tween these supplies and noise will be coupled through parasitic capacitances. if isolated power supplies are derived from a common trans- former interwinding capaci- tance should be minimized. iii. keep printed circuit board traces between the interface circuit and ipm short. long traces have a tendency to pick up noise from other parts of the circuit. iv. use recommended decoupling capacitors for power supplies and optocouplers. fast switch- ing igbt power circuits gener- ate dv/dt and di/dt noise. every precaution should be taken to protect the control circuits from coupled noise. v. use shielding. printed circuit board shield layers are helpful for controlling coupled dv/dt noise. figure 6.37 shows an example of how the primary and secondary sides of the iso- lating interface can be shielded. vi. high speed optocouplers with high common mode rejection (cmr) should be used for sig- nal input: t plh ,t phl < 0.8 m s cmr > 10kv/ m s @ v cm = 1500v appropriate optocoupler types are hcpl 4503, hcpl 4504 (hewlett packard) and ps2041 (nec). usually high speed optos require a 0.1 m f decoupling capacitor close to the opto. vii. select the control input pull-up resistor with a low enough value to avoid noise pick-up by the high impedance ipm input and with a high enough value that the high speed optotransistor can still pull the ipm safely below the recom- mended maximum v cin(on) . figure 6.36 isolated interface circuit for dual intelligent power modules 1 hcpl4504 0.1 m f c 1 v 1 (+) p s r (+5) c in f o v c (-) v 1 (+) n c1 dual ipm s r (+5) c in c i f o v c (-) + 6.8k 0.1 m f 6.8k 2 3 4 8 7 6 5 3 pc817 4 2 1 1 hcpl4504 2 3 4 8 7 6 5 3 pc817 4 3 2 2.2 m f 47 m f 50v 330 m f 50v 1 7521 12 113-400 vdc 11 6 5 - + + + + + + 4 14 n fo n in p fo p in 13 12 11 10 v in 9 8 7 +15 0 +15 0 +15 0 +15 0 2 1 m57120l 1 2 3 4 5 1 2 3 4 5 mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 figure 6.37 interface circuit layout example for dual ipms w n v n u n w p v p u p + - + - + - + - + - + - f o w n f o w p f o v n v p f o u n f o u p f o shields ground to negative side of each control power supply digital ground mid-layer shield to control power source w v u legend top layer middle layer bottom layer shield ground to v unc shield ground to v upc shield ground to v vnc shield ground to v vpc shield ground to v wnc shield ground to v wpc mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 viii.if some ipm switches are not used in actual application their control power supply must still be applied. the related signal input terminals should be pulled up by resistors to the control power supply (v d or v sxr ) to keep the unused switches safely in off-state. ix. unused fault outputs must be tied high in order to avoid noise pick up and unwanted activa- tion of internal protection cir- cuits. unused fault outputs should be connected directly to the +15v of local isolated con- trol power supply. 6.6.3 example interface circuits ipm (intelligent power modules) are designed to use optocoupled transistors for control input and fault output interfaces. in most ap- plications optocouplers will provide a simple and inexpensive isolated interface to the system controller. figures 6.39 through 6.43 show ex- ample interface circuits for the four ipm power circuit configurations. these circuits use two types of optocoupled transistors. the con- trol input on/off signals are trans- ferred from the system controller using high speed optocoupled tran- sistors. usually high speed optos require a 0.1 m f film or ceramic decoupling capacitor connected near their v cc and gnd pins. the value of the control input pull up re- sistor is selected low enough to avoid noise pick up by the high im- pedance input and high enough so that the high speed optotransistor with its relatively low current trans- fer ratio can still pull the input low enough to assure turn on. the cir- cuits shown use a hewlett packard hcpl-4504 optotransistor. this opto was chosen mainly for its high common mode transient immunity of 15,000v/ m s. for reliable opera- tion in igbt power circuits optocouplers should have a mini- mum common mode noise immu- nity of 10,000 v/ m s. low speed optocoupled transistors can be used for the fault output and brake input. slow optos have the added advantages of lower cost and higher current transfer ratios. the example interface circuits use a sharp pc817 low speed optocoupled transistor for the transfer of brake and fault signals. like most low speed optos the pc817 does not have internal shielding. some switching noise will be coupled through the opto. an rc filter with a time constant of about 10ms can be added to the optos output to remove this noise. the ipms 1.5ms long fault output signal will be almost unaffected by the addition of this filter. when de- signing interface circuits always fol- low the interface circuit layout guidelines given in section 6.6.2. figure 6.38 interface circuit layout for a v-series ipms bpn uv w ipm ipm interface circuit pcb mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 figure 6.39 interface circuit for seven-pack ipms n p b u v w line motor + c s v upc uf o u p v up1 v vpc vf o v p v vp1 v wpc wf o w p v wp1 v nc v n1 b r u n v n w n f o 7-pack third generation ipm 10 m f 20k 0.1 m f 15 v + fault u p interface input 15 v + 15 v + 15 v + v p interface w p interface n side interface fault output input brake u n input v n input w n input fault 0.1 m f 0.1 m f 0.1 m f 33 m f 20k 4.7k 20k 20k same as u p interface circuit same as u p interface circuit fault output input rated decoupling applicable current capacitor types (amps) (c s ) 600v modules pm30rsf060 30 0.3 m f pm50rsk060 55 0.47 m f pm50rsa060 50 0.47 m f pm75rsa060, 75 1.0 m f pm75rsk060, pm75rva060 pm100rsa060 100 1.0 m f pm150rsa060 150 1.5 m f pm200rsa060 200 2.0 m f 1200v modules pm10rsh120 10 0.1 m f pm15rsh120 15 0.1 m f pm25rsb120, 25 0.22 m f pm25rsk120 pm50rsa120, 50 0.47 m f pm50rva120 note: if high side fault outputs are not used, they must be connected to the +15v of the local power supply. mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 figure 6.40 interface circuit for six-pack ipms n p u v w line motor + c s v upc uf o u p v up1 v wpc vf o v p v vp1 wf o v wp1 v nc v n1 u n v n w n f o 6-pack third generation ipm 10 m f 20k 0.1 m f 15 v + fault u p interface input 15 v + 15 v + 15 v + v p interface w p interface n side interface fault output input u n input v n input w n input fault 0.1 m f 0.1 m f 0.1 m f 33 m f 20k 20k 20k same as u p interface circuit v wpc w p same as u p interface circuit fault output input rated decoupling applicable current capacitor types (amps) (c s ) 600v modules pm10csj060 10 0.1 m f pm15csj060 15 0.1 m f PM20CSJ060 20 0.1 m f pm30csj060 30 0.3 m f pm100csa060, 100 1.0 m f pm100cva060 pm150csa060, 150 1.5 m f pm150cva060 pm200csa060, 200 2.2 m f pm200cva060 pm300cva060 300 3.0 m f 1200v modules pm75csa120, 75 1.0 m f pm75cva120 pm100csa120, 100 1.0 m f pm100cva120 pm150cva120 150 1.5 m f note: unused fault outputs must be connected to the +15v of the local control supply. mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 figure 6.41 interface circuit for dual ipms c 2 6.8k + c 2 c 2 15 v 15 v 15 v 15 v 15 v v cc w v u motor ipm + + + + + ipm ipm input fault + + 0.1 m f 0.1 m f 6.8k c 1 + c 1 + 15 v f no v nc c ni s nr v n1 f po v pc c pi s pr v p1 f no v nc c ni s nr v n1 f po v pc c pi s pr v p1 f no v nc c ni s nr v n1 f po v pc c pi s pr v p1 e 1 c 2 c 1 e 2 e 1 c 2 c 1 e 2 e 1 c 2 c 1 e 2 input fault control power rated decoupling snubber applicable current capacitor capacitor types (amps) (c 1 )(c 2 ) 600v modules pm200dsa060 200 47 m f 2.0 m f pm300dsa060 300 47 m f 3.0 m f pm400dsa060, 400 68 m f 4.0 m f pm400dva060 pm600dsa060, 600 68 m f 6.0 m f* pm600dva060 1200v modules pm75dsa120 75 22 m f 0.68 m f pm100dsa120 100 47 m f 1.5 m f pm150dsa120 150 47 m f 2.0 m f pm200dsa120, 200 68 m f 3.0 m f pm200dva120 pm300dsa120, 300 68 m f 5.0 m f pm300dva120 *depending on maximum dc link voltage and main circuit layout, an rcdi clamp may be needed. (see section 3.3) mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 control power main bus rated decoupling snubber decoupling applicable current capacitor capacitor capacitor types (amps) (c 1 )(c 2 )(c 3 ) snubber diode 600v modules pm800hsa060 800 68 m f 3.0 m f 6.0 m f rm50hg-12s (2 pc. parallel) 1200v modules pm400hsa120 400 68 m f 1.5 m f 4.0 m f rm25hg-24s pm600hsa120 600 68 m f 2.0 m f 6.0 m f rm25hg -24s (2 pc. parallel) pm800hsa120 800 68 m f 3.0 m f 6.0 m f rm25hg-24s (3 pc. parallel) figure 6.42 interface circuit for single ipms + + 15 v 6.8k ipm 0.1 m f c 1 input fault v 1 s r c 1 c 2 v c c e d f o + + 15 v 6.8k ipm 0.1 m f c 1 v 1 s r c 1 v c c e f o c 2 c 3 c 3 c 3 d ipm v 1 s r c 1 c 2 v c c e d f o ipm v 1 s r c 1 v c c e f o c 2 d ipm v 1 s r c 1 c 2 v c c e d f o ipm v 1 s r c 1 v c c e f o c 2 d + + + 15v + v cc + motor uvw input fault 15v 15v 15v mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 figure 6.43 interface circuit for pm10czf120 and pm15czf120 0.1 m 0.1 m 10 m + e 20k 20k v wp w p v wpc u n v n w n v n1 f o v nc i f v d3 v d3 v d4 5v 10k 0.1 m 10 m + e 20k v vp v p v vpc i f v d2 0.1 m 10 m + e 20k v up u p v upc i f v d1 i f 0.1 m 20k i f 0.1 m 20k i f 33 m + e m c s p u v w n + e v cc mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.6.4 connecting the interface circuit the input pins of mitsubishi intelli- gent power modules are designed to be connected directly to a printed circuit board. noise pick up can be minimized by building the interface circuit on the pcb near the input pins of the module. low power modules have tin plated control and power pins that are de- signed to be soldered directly to the pcb. higher power modules have gold plated pins that are de- signed to be connected to the pcb using an inverse mounted header receptacle. an example of this con- nection for a dual type ipm is shown in figure 6.44. this connec- tion technique can also be adapted to large six and seven pack mod- ules. table 6.7 shows the sug- gested connection method and connector for each third genera- tion ipm. table 6.8 shows the suggested connection method and connector for v-series ipms. figure 6.45 shows the pcb layout for v-series six and seven pack connector. figure 6.44 connection of the interface circuit a b c d e hole for header receptacle pin clearance hole for ipm pin clearance hole for ipm guide pin ipm pin spacing header receptacle pin spacing .040" typ. .070" typ. .090" typ. 0.10" typ. per connector mfg. a c b side view end view e d header receptacle printed circuit board ipms guide pins c 1 pcb layout example for dual type 3rd generation ipm table 6.7 third generation ipm connection methods third generation intelligent power module type connection method pm10csj060, pm15csj060, PM20CSJ060, solder to pcb pm30csj060, pm30rsf060, pm50rsk060, pm10rsh120, pm15rsh120 pm50rsa060, pm75rsa060, pm100csa060, 31 position 2mm inverse header pm100rsa060, pm150csa060, pm150rsa060, receptacle pm200csa060, pm25rsb120, pm50rsa120, hirose p/n: df10-31s-2dsa (59) pm75csa120, pm100csa120 pm200dsa060, pm300dsa060, pm400dsa060, 5 position 2.54mm (0.1") inverse pm600dsa060, pm75dsa120, pm100dsa120, header receptacle pm150dsa120, pm200dsa120, pm300dsa120, method p/n: 1000-205-2105 pm400hsa120, pm600hsa120 hirose p/n: mdf7-5s-2.54dsa mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.6.5 dead time (t dead ) in order to prevent arm shoot through a dead time between high and low side input on signals is required to be included in the sys- tem control logic. two different val- ues are specified on the datasheet: a. t dead measured directly on the ipm input terminals b. t dead related to optocoupler input signals using the recommended application circuit the specified type b dead time is related to standard high speed optocouplers. (see section 6.6.2) by using specially selected optocouplers with narrow distribu- tion of switching times the required type b dead time could be reduced. 6.6.6 using the fault signal in order to keep the interface cir- cuits simple the ipm uses a single on/off output to alert the system controller of all fault condi- tions. the system controller can easily determine whether the fault signal was caused by an over tem- perature or over current/short cir- cuit by examining its duration. short circuit and over current con- dition fault signals will be t fo (nominal 1.5ms) in duration. an over temperature fault signal will be much longer. the over temperature figure 6.45 pcb layout for v-series connector fault starts when the base plate temperature exceeds the ot level and does not reset until the base plate cools below the ot r level. typically this takes tens of sec- onds. note: unused fault outputs must be prop- erly terminated by connecting them to the +15v on the local control power supply. failure to properly terminate unused fault outputs may result in unexpected tripping of the modules internal protection. 3 0.05 3 0.05 3 0.05 3 0.05 3 0.05 43.57 0.1 19 - ?1.2 +0.1 0 19 - ?0.9 +0.1 0 4 - ?3.2 +0.1 -0.07 14.1 0.05 14.1 0.05 2.54 0.05 2.54 0.05 14.1 0.05 14.6 0.1 table 6.8 v-series ipm connection methods v-series intelligent power module type connection method pm75rva060, pm100cva060, pm150cva060, 19 position, 0.1" compound pm200cva060, pm300cva060, pm50rva120, inverse header receptacle, pm75cva120, pm100cva120, pm150cva120 hirose part # mdf92-19s-2.54dsa pm400dva060, pm600dva060, 5 position, 0.1" (2.54mm) pm200dva120, pm300dva120 inverse header receptacle, hirose part # mdf7-5s-2.54dsa mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.7 ipm inverter example the ipms integrated intelligence greatly simplifies inverter design. the built in protection circuits allow maximum utilization of power de- vice capability without compromis- ing reliability. figure 6.46 shows a complete inverter constructed us- ing dual type ipms. input common mode noise filtering and mov surge suppression helps to protect the input rectifier and ipms from line transients. the main power bus is constructed using laminated plates in order to minimize parasitic inductance. low inductance bus designs are covered in more detail in sections 3.2 and 3.3. an ex- ample of the mechanical layout of the inverter is shown in figure 6.47. the ipms must be mounted on a heatsink with suitable cooling capabilities. thermal design and power loss estimation is covered in section 3.4. mitsubishi offers a complete line-up of diode modules that are ideal for use as the input bridge in inverter applications. figure 6.46 ipm inverter system + C rectifier bridge a c b c c c heat sink ground ipm + ipm ipm printed circuit board containing interface circuits and isolated power supplies micro-controller pwm generator input common mode noise filter and mov surge protection c ? 470pf style 2 & 3 c ? 2200pf style 1 main filter 3-phase input laminated bus structure u vw to load (3-phase motor) s snubber s s s figure 6.47 power circuit layout for ipms control printed circuit board snubber circuit heat sink copper-insulator-copper sandwich capacitor mitsubishi semiconductors power modules mos using intelligent power modules
sep.1998 6.8 handling precautions for intelligent power modules electrical considerations: i. apply proper control voltages and input signals before static testing. ii. carefully check wiring of con- trol voltage sources and input signals. miswiring may destroy the integrated gate control cir- cuit. iii. when measuring leakage cur- rent always ramp the curve tracer voltage up from zero. ramp voltage back down be- fore disconnecting the device. never apply a voltage greater than the v ces rating of the device. iv. when measuring saturation voltage low inductance test fix- tures must be used. inductive surge voltages can exceed de- vice ratings. mechanical considerations: i. avoid mechanical shock. the module uses ceramic isolation that can be cracked if the mod- ule is dropped. ii. do not bend the power termi- nals. lifting or twisting the power terminals may cause stress cracks in the copper. iii. do not over torque terminal or mounting screws. maximum torque specifications are pro- vided in device data sheets. iv. avoid uneven mounting stress. a heatsink with a flatness of 0.001"/1" or better is recom- mended. avoid one sided tight- ening stress. figure 6.48 shows the recommended torquing order for mounting screws. uneven mounting can cause the modules ceramic isolation to crack. thermal considerations: i. do not put the module on a hot plate. externally heating the module's base plate at a rate greater than 15 c/min. will cause thermal stress that may damage the module. ii. when soldering to the signal pins and fast on terminals avoid excessive heat. the sol- dering time and temperature should not exceed 230 c for 5 seconds. iii. maximize base plate to heatsink contact area for good heat transfer. use a thermal in- terface compound such as white silicon grease. the heatsink should have a surface finish of 64 microinches or less. figure 6.48 mounting screws torque order 2 1 4 1 2 3 mitsubishi semiconductors power modules mos using intelligent power modules

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